B. Kuo, “Floating-Muscles Kink-Feeling Relevant Capacitance Decisions out-of Nanometer PD SOI NMOS Gizmos” , EDMS , Taiwan

71. Grams. S. Lin and J. B. Kuo, “Fringing-Triggered Narrow-Channel-Effect (FINCE) Related Capacitance Choices of Nanometer FD SOI NMOS Equipment Playing with Mesa-Separation Via three dimensional Simulator” , EDSM , Taiwan ,

72. J. B. Kuo, “Development off Bootstrap Approaches to Low-Current CMOS Digital VLSI Circuits getting SOC Programs” , IWSOC , Banff, Canada ,

P. Yang, “Gate Misalignment Perception Associated Capacitance Decisions regarding an excellent 100nm DG FD SOI NMOS Tool that have n+/p+ Poly Better/Base Entrance” , ICSICT , Beijing, China

73. Grams. Y. Liu, Letter. C. Wang and you will J. B. Kuo, “Energy-Successful CMOS Highest-Weight Driver Circuit on Subservient Adiabatic/Bootstrap (CAB) Technique for Low-Electricity TFT-Lcd System Software” , ISCAS , Kobe, Japan ,

74. Y. S. Lin, C. H. Lin, J. B. Kuo and you can K. W. Su, “CGS Capacitance Event off 100nm FD SOI CMOS Gadgets having HfO2 High-k Gate Dielectric Considering Vertical and you can Fringing Displacement Consequences” , HKEDSSC , Hong-kong ,

75. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Relevant Capacitance Conclusion of good 100nm DG SOI MOS Devices which have Letter+/p+ Top/Bottom Door” , HKEDSSC , Hong kong ,

76. Grams. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Productive CMOS Highest-Weight Rider Circuit to the Complementary Adiabatic/Bootstrap (CAB) Technique for Reduced-Fuel TFT-Liquid crystal display Program Software” , ISCAS , Kobe, The japanese ,

77. H. P. Chen and you may J. B. Kuo, “Good 0.8V CMOS TSPC Adiabatic DCVS Reason Routine on the Bootstrap Techniques for Low-Electricity VLSI” , ICECS , Israel ,

B. Kuo, “A novel 0

80. J. B. Kuo and you will H. P. Chen, “A low-Current CMOS Weight Driver to the Adiabatic and you can Bootstrap Techniques for Low-Strength System Programs” , MWSCAS , Hiroshima, The japanese ,

83. M. T. Lin, E. C. Sunrays, and you can J. B. Kuo, “Asymmetric Entrance Misalignment Influence on Subthreshold Functions DG SOI NMOS Gizmos Offered Fringing Electric Field effect” , Electron Gizmos and Issue Symposium ,

84. J. B. Kuo, Age. C. Sunshine, and you may Meters. T. Lin, “Study from Entrance Misalignment Affect the latest Tolerance Voltage regarding Double-Entrance (DG) Ultrathin FD SOI NMOS Equipment Playing with a compact Model Provided Fringing Digital Field effect” , IEEE Electron Gizmos having Microwave and you will Optoelectronic Programs ,

86. Age. Shen and J. 8V BP-DTMOS Stuff Addressable Thoughts Cell Circuit Produced from SOI-DTMOS Procedure” , IEEE Meeting into the Electron Equipment and you will Solid state Circuits , Hong-kong ,

87. P. C. Chen and you may J. B. Kuo, “ic Reasoning Routine Having fun with a primary Bootstrap (DB) Way of Reasonable-current CMOS VLSI” , All over the world Symposium to your Circuits and you may Expertise ,

89. J. B. Kuo and you can S. C. Lin, “Compact Breakdown Model getting PD SOI NMOS Gizmos Offered BJT/MOS Impact Ionization to possess Liven Circuits Simulation” , IEDMS , Taipei ,

ninety. J. B. Kuo and you will S. C. Lin, “Lightweight LDD/FD SOI CMOS Device Model Provided Energy Transportation and Thinking Temperatures having Liven Routine Simulator” , IEDMS , Taipei ,

91. S. C. Lin and you will J. B. Kuo, “Fringing-Induced Burden Reducing (FIBL) Effects of 100nm FD SOI NMOS Products with high Permittivity Gate Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Meeting Proc , Williamsburg ,

ninety five. J. B. Kuo and S. C. Lin, “The latest Fringing Digital Field-effect into the Short-Station Impact Threshold Voltage out-of FD SOI NMOS Gizmos with LDD/Sidewall Oxide Spacer kissbrides.com click this site Construction” , Hong kong Electron Equipment Appointment ,

93. C. L. Yang and you will J. B. Kuo, “High-Temperatures Quasi-Saturation Make of Higher-Voltage DMOS Strength Gadgets” , Hong-kong Electron Equipment Conference ,

94. Age. Shen and you can J. B. Kuo, “0.8V CMOS Stuff-Addressable-Recollections (CAM) Mobile Ciurcuit having a quick Tag-Compare Effectiveness Playing with Most PMOS Active-Tolerance (BP-DTMOS) Technique Based on Fundamental CMOS Technical for Lower-Current VLSI Solutions” , Internationally Symposium into the Circuits and you may Expertise (ISCAS) Procedures , Arizona ,

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